Programming Massively Parallel Hardware (PMPH)

Course content

The aim of the course is to teach students how to efficiently and effectively exploit parallel hardware, which is now mainstream (i.e., how to quickly write programs that run fast).

The course reviews the levels at which hardware exposes parallelism, the constraints at each level, the main tradeoffs and the potential bottlenecks, and studies the critical components of parallel hardware: processor, memory (cache) hierarchy and interconnect networks.

The course introduces the map-reduce programming model, which is used to fully express available parallelism, and to reason about asymptotic properties of parallel programs (in terms of work and depth). The course then introduces several lower-level programming interfaces, such as OpenMP, OpenCL, and gives practical instructions to implementing, testing, and optimizing parallel programs written in these interfaces.

Finally, the course highlights how hardware differences influence the way in which the program is optimized, and studies several composible code transformations that have been found effective to implement parallelism. These can be seen as recipes for optimizing the application's degree of parallelism and locality of reference.


MSc Programme in Computer Science
MSc Programme in Bioinformatics

Learning outcome

Knowledge of

  • the main differences in various parallel hardware, and how these influence the way the code is optimized/tuned.
  • the (in)correctness of (specific instances of) loop parallelization and related optimizations.
  • how to guide, in specific instances, the application of such optimizations, and the (data-sensitive) tradeoffs that are exploited.

Skills in

  • implementing parallel programs using different programming interfaces, such as OpenMP, CUDA.
  • testing, profiling, and tuning the programs to efficiently take advantage of the parallel hardware (multicore, GPU).

Competences in

  • identifying an effective parallelization solution for a given application and/or parallel hardware.


Lectures, in-class exercises, group work on programming and analysis assignments and project.

The course does not use a textbook, but instead provides tutorials, scientific papers, and selected material from several books (available from the course pages).
For example, several hardware-related topics were selected from the book Parallel Computer Organization and Design, by Michel Dubois, Murali Annavaram and Per Stenstrom,  ISBN 978-521-88675-8. Cambridge University Press, 2012.  

The course syllabus assumes basic knowledge of hardware architecture, programming languages, compilers, data-structures and algorithms, linear algebra, and most importantly programming competences in C/C++ (and optionally Haskell). For example, at DIKU, these can be acquired through the corresponding BSc courses (or through self study).

7,5 ECTS
Type of assessment
Continuous assessment
Four individual assignments (40%), group project (report) with individual presentation and short oral examination (60%). No aids are allowed for the oral examination.
All aids allowed
Marking scale
7-point grading scale
Censorship form
No external censorship
several internal examiners
Criteria for exam assessment

See Learning Outcome.

Single subject courses (day)

  • Category
  • Hours
  • Lectures
  • 32
  • Preparation
  • 48
  • Exercises
  • 61
  • Project work
  • 64
  • Exam
  • 1
  • English
  • 206